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freescale semiconductor application note AN2903 rev. 6, 10/2007 ? freescale semiconductor, inc., 2004, 2007. all rights reserved. this application note provides a set of recommendations to assist you in a first-time design with the msc8126 device. this document can also be useful as a general guideline for designing new systems because it highlights the aspects of a design that merit special attention during initial system start-up. 1 getting started during the first phase of designing a system with the msc8126 device, your main tasks are to make the pin assignments and configure the reset parameters. before you get started, you should be familiar with the available documentation, silicon revisions, software, models, and tools. refer to section 9 , related reading, on page 18 . 1.1 pin assignments some msc8126 pins are multiplexed, depending on the device programming. take care in programming msc8126 registers to configure these multiplexed pins as needed for your system design. a signal function should be routed to a single pin, so any other pins providing that signal functionality should have it turned off. pin multiplexing is configured in the following registers: ? hard reset configuration word (hrcw) ? siu module configuration register (siumcr) ? memory controller registers orx and brx ? gpio port registers. contents 1 getting started.............................................................1 1.1 pin assignments ..........................................................1 1.2 configuring reset parameters .....................................2 2 power ...........................................................................4 3 clocks ..........................................................................5 4 reset ............................................................................5 4.1 power-on-reset circuit...............................................5 4.2 reset configuration pins .............................................6 4.3 boot..............................................................................7 5 bit and byte lane ordering.........................................8 6 memory .......................................................................9 6.1 60x bus signals and memory transactions ................9 6.2 baddrx in 60x mode ..............................................10 6.3 bank selects versus address lines...........................10 6.4 bank versus page interleaving..................................10 7 eonce/jtag interface.............................................10 8 signal terminations...................................................12 9 related reading.........................................................18 msc8126 design checklist by tina redheendran
msc8126 design checklist, rev. 6 2 freescale semiconductor getting started some signals have one function during reset but switch to another multiplexed function during regular operation. these signals include swte , dsisync , dsi64 , modck[1?2] , and cnfgs . these signals switch to dsi functionality after the system exits the reset state. ta b l e 1 shows an overview of the multiplex options for the tdm interface, dsi bus, system bus, and ethernet controller. the pins are chosen based on the settings of the dsi reset configuration pin, the ethsel bit in the hard reset configuration word, and the en and ifmode bits in the ethernet miigsk configuration registers. there are two options for the location of the ethernet pins: exposed on the low part of the dsi/system bus or exposed on the gpio pins. even though the pins are repeated in each option, the options cannot be mixed. all ethernet pins must be from the dsi/system bus or from the gpio pins. you cannot choose some of the ethernet pins from the dsi/system bus and the others from the gpio pins. the smii mode of the ethernet controller is available only on the gpio pins. table 1 also indicates which tdms are available on the gpio pins when the different ethernet options are chosen. 1.2 configuring reset parameters review the hrcw to determine initial power-on-reset parameters, such as single msc8126 bus mode versus 60x?compatible bus mode, boot port size, and on, and then set the bits for your application (see table 2 ). table 1. multiplexing overview configuration pins dsi64 (reset pin) ethsel (hrcw) en (miigsk_enr) ifmode (miigsk_cfgr) tdms available dsi bus width system bus width ethernet on dsi/system bus ethernet on gpio pins 0 0 0 xx 0,1,2,3 32 bit 64 bit ? ? 0 0 1 00 0,1 32 bit 64 bit ? mii 0 0 1 10 0,1,3 32 bit 64 bit ? rmii 0 0 1 01 0,1,3 32 bit 64 bit ? smii 0 1 0 xx 0,1,2,3 32 bit 32 bit ? ? 0 1 1 00 0,1,2,3 32 bit 32 bit mii ? 0 1 1 10 0,1,2,3 32 bit 32 bit rmii ? 0 1 1 01 0,1,2,3 32 bit 32 bit ? ? 1 0 0 xx 0,1,2,3 64 bit 32 bit ? ? 1 0 1 00 0,1 64 bit 32 bit ? mii 1 0 1 10 0,1,3 64 bit 32 bit ? rmii 1 0 1 01 0,1,3 64 bit 32 bit ? smii 1 1 x xx 0,1,2,3 64 bit 32 bit ? ?
getting started msc8126 design checklist, rev. 6 freescale semiconductor 3 table 2. hard reset configuration word (hrcw) name reset description settings earb 0 0 external arbitration defines the initial value for acr[earb]. 0 internal arbitration is performed. 1 external arbitration is assumed. exmc 1 0 external memc defines the initial value of br0[ememc]. 0 no external memory controller is assumed. 1 external memory controller is assumed. intout 2 0 int_out or irq7 selection defines the initial value of siumcr[intout]. 0 irq7 / int_out is irq7 . 1 irq7 / int_out is int_out . ebm 3 0 external 60x-compatible bus mode defines the initial value of bcr[ebm]. 0 single msc8126 bus mode. 1 60x-compatible bus mode. bps 4?5 00 boot port size defines the initial value of br0[ps], the port size for memory controller bank 0. 00 64-bit port size. 01 8-bit port size. 10 16-bit port size. 11 32-bit port size. scdis 6 0 sc140 cores disabled enables/disables the sc140 cores. 0 sc140 cores enabled. 1 sc140 cores disabled. isps 7 0 internal space port size defines the initial value of bcr[isps]. setting isps enables a 32-bit master to access the msc8126 internal space. 0 msc8126 acts as a 64-bit slave to external masters access to its internal space. 1 msc8126 acts as a 32-bit slave to external masters access to its internal space. irpc 8 0 interrupt pin configuration defines the initial value of siumcr[irpc]. 0 irq2 , irq3 , irq5 active. 1 baddr29, baddr30, baddr31 active. ? 9 0 reserved. cleared to zero for future compatibility. dppc 10?11 00 data parity pin configuration defines the initial value of siumcr[dppc]. 00 irq[1?7] active. 01 dp[0?7] active. 10 dreq[1?4], dack[1?4] active. 11 ext_br[2?3] , ext_bg[2?3], ext_dbg[2?3] , and irq[6?7] active. nmi out 12 0 nmi out defines whether the host or one of the sc140 cores handles a non-maskable interrupt (nmi) event. 0 nmi is serviced by sc140 cores. 1 nmi is routed to nmi_out and serviced by the external host. isbsel 13?15 000 initial internal space base select defines the initial value of immr[isb], which determines the base address of the internal memory space. the sc140 internal address space spans from 0x00000000 ? 0x00ffffff (16 mb). therefore it is not advisable to map the immr in this space, since the sc140s cannot access the siu registers. 000 0xf0000000. 001 0xf0f00000. 010 0xff000000. 011 0xfff00000. 100 reserved. this option should not be used. 101 reserved. this option should not be used. 110 0x0f000000. 111 0x0ff00000.
msc8126 design checklist, rev. 6 4 freescale semiconductor power 2power this section outlines the msc8126 power supply and power consumption considerations. for information on ac/dc electrical specifications, thermal characteristics, start-up, and power sequencing, refer to the data sheet. ? power supply . the msc8126 has a core voltage, v dd , that operates at a lower voltage than the i/o voltage v ddh . you should supply the msc8126 core voltage v dd via a variable power supply (switching supply or regulator) to allow for future compatibility with possible core voltage changes on future silicon revisions. the core voltage is supplied across v dd and v ss ( gnd ). the core supply voltage must be between 1.14 v and 1.26 v for 400 mhz devices. the core supply voltage must be between 1.16 v and 1.24 v for 500 mhz devices. bbd 17 0 bus busy disable defines the initial value of siumcr[bbd]. 0 abb , dbb active. 1 irq[4?5] active. mmr 18 0 mask masters requests defines the initial value of siumcr[mmr]. 0 no masking on bus request lines. 1 all external bus requests masked (boot master is the one of the internal cores). ethsel 19 0 ethernet select defines whether the ethernet is exposed on the low part of the dsi/60x data bus lines (when ethsel is set and the dsi64 line is sampled low at reset) or the gpio lines (when ethsel is clear). ttpc 20 0 transfer type pin configuration defines the initial value of siumcr[ttpc]. 0 tt[0, 2?4] active. 1 cs[5?7] active. cs5pc 21 0 chip select 5 pin configuration defines the initial value of siumcr[cs5pc]. 0 cs5 active. 1 bctl1 active. tcpc 22?23 0 transfer code pin configuration defines the initial value of siumcr[tcpc]. 00 tc[0?2] active. 10 bnksel[0?2] active. ltlend 24 0 little endian defines the host endian mode of operation. 0 big-endian. 1 little-endian. ppcle 25 0 munged little endian when the ltlend bit is set, ppcle specifies whether the host is a little-endian host or a host that works in munged little-endian mode. 0 true little-endian host. 1 munged little-endian host. ? 26 0 reserved. cleared to zero for future compatibility. ? 27 1 reserved. must be set to 1. modck[3?5] 28?30 0 modck high order bits high-order bits of the modck bus, which determine the clock reset configuration. refer to the chapter on clocks in the msc8126 reference manual . ? 31 0 reserved. cleared to zero for future compatibility. table 2. hard reset configuration word (hrcw) (continued) name reset description settings
clocks msc8126 design checklist, rev. 6 freescale semiconductor 5 the i/o section of the msc8126 is supplied with 3.3 v ( 5%) across v ddh and v ss ( gnd ). typically, this voltage is supplied by a simple linear regulator, which increases system complexity because multiple power supplies are required for the design. external signals on the msc8126 are not 5 v tolerant. all input signals must meet the v in dc spec (?0.2 v to v ddh + 0.2). after the power-up sequence, v ddh must not exceed v dd / v ccsyn by more than 2.6 v. for details on supply design considerations, consult the msc8126 technical data sheet and the application note entitled msc8122 and msc8126 power circuit design recommendations and examples (an2937). ? power consumption. the msc8126 technical data sheet provides preliminary power dissipation estimates for various configurations. you can take the following steps to reduce power consumption in your design: ? stop mode for sc140 cores . any sc140 core can be placed into stop mode when it is not in use. however, the core can be taken out of stop mode only through a device reset such as poreset , hreset , or sreset . ? wait mode for sc140 cores . any sc140 core can be placed into wait mode when it is not in use. the sc140 core exits wait mode when there is an interrupt request as well as a reset or debug request. ? clkout disable . if the system bus clock output is not needed in a system design, it can be masked by setting the siumcr[clkod] bit. masking the clock output not only reduces power consumption but also noise in the design. ? disable unused ip peripherals . all ip bus peripherals have a control bit to mask their clock. any unused peripherals should be programmed to stop mode. for details, see the ipbus chapter of the msc8126 reference manual . 3clocks all inputs and outputs except those associated with a serial clock are referenced to refclk. there are two modes for clock distribution, back-compatibility (with the msc8102 device) and pll skew elimination mode. pll skew elimination is the recommended mode. in this mode, the refclk is clkin , which is clocked by an on- board oscillator. the clock mode is determined by the clock mode settings, as follows: ? modck[1?2] . the modck[1?2] pins are sampled at the rising edge of poreset while hreset is still asserted. their value can be set using pull-ups/pull-downs. therefore, open collector drivers are not needed. ? modck[3?5] . modck[3?5] can be set in the hrcw, or you can take the default value. collectively, the modck[3?5] and modck[1?2] fields define the multiplication of the input clock ( clkin ) to derive the sc140 core and system bus clock ratios. note that the spll multiplication value is set only during an initial hreset caused by a poreset , so the spll does not change during subsequent assertions of hreset . refer to the msc8126 reference manual for the most up-to-date clock configuration mode tables. 4 reset this section describes the reset recommendations for configuring the msc8126 device at reset. 4.1 power-on-reset circuit there is no power-up detector on the msc8126 device. optionally, a power-on-reset chip to monitor the power plane and drive poreset can be used. poreset must be asserted externally for at least 16 clkin cycles after external power to the msc8126 reaches nominal value.
msc8126 design checklist, rev. 6 6 freescale semiconductor reset hreset is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain device. for an open-drain output such as hreset , take care when driving many buffers that implement input bus- hold circuitry. the bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic level to low. either a smaller value of pull-up or less current loading from the bus-hold drivers overcomes this issue. to avoid exceeding the msc8126 output current, the pull-up value should not be too small (a 1 k pull-up is used in the msc8126ads reference design). sreset is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain device. the msc8126 device drives sreset if the poreset line or the hreset line is asserted. a software watchdog time-out, bus monitor time-out, jtag reset, or external soft reset can also drive sreset . 4.2 reset configuration pins the default hrcw (0x00000000) can be taken by connecting cnfgs to 0 and rstconf to a logic 1 on the rising edge of poreset . in this case, no accesses are made to the prom connected to cs0 . the default case for the device is single msc8126 mode. if the configuration word is not written via the 60x system bus during 1024 clkin cycles, the msc8126 gets the default configuration word value. initial values other than the default can be obtained by selecting a different combination for the cnfgs and rstconf pins. bctl0 is active (functioning as w/ r ) during the hrcw write. take care to avoid bus contention during this time if buffers on the board are under bctl0 control. bctl1 should not be used during the reset configuration procedure. ta b le 3 shows the reset configuration mode options. for details, refer to the reset chapter of the msc8126 reference manual . if both cnfgs and rstconf are pulled to logic 0 on the rising edge of poreset , the msc8126 device is a configuration master. the hrcw is read from the prom connected to cs0 at addresses 0x00, 0x08, 0x10, and 0x18. these four bytes are written to the fields of the hrcw. the msc8126 device can act as a configuration master to configure up to seven msc810x configuration slaves by individually connecting the rstconf lines of up to seven slaves to the most significant seven address bits of the configuration master address bus. the master continues to read bytes starting at 0x20, configures the next slave while driving the rstconf line of the slave, and writes a 32-bit configuration word to that slave while the master drives the hreset asserted to the slave. this process is repeated from addresses 0x40, 0x60, 0x80, 0xa0, 0xc0, and 0xe0 for the remaining six slaves. the configuration master drives the full 32-bit configuration word on the 60x data bus after each 4-byte read from the prom. avoid any contention on the bus that would affect the configuration word. no pull-ups are required on the address bus because it is actively driven during this operation. if cnfgs is logic 1 and rstconf is pulled to logic 0 on the rising edge of poreset , the msc8126 slave can be configured to receive the hrcw via the dsi. the host drives the hcid[0?3] signals to indicate which msc8126 slave it is configuring. these signals can be driven by the host address lines. alternatively, the host can write the hrcw to all msc8126 slaves at once using the host broadcast chip select ( hbcs ). the msc8126 slave remains in reset state until it receives its hrcw. table 3. reset configuration modes cnfgs, rstconf reset configuration word source 00 reset configuration via system bus. msc8126 is the configuration master. 01 reset configuration via system bus. msc8126 is the configuration slave. 10 reset configuration via write through dsi. 11 reserved.
reset msc8126 design checklist, rev. 6 freescale semiconductor 7 4.3 boot the msc8126 boots from memory on the system bus, a host on the system bus, a host via the direct slave interface (dsi), or via the time-division multiplexing module (tdm), universal asynchronous receiver/transmitter (uart), or i 2 c ports. the boot source is determined by the state of the bm[0?2] signals sampled at the rising edge of poreset (see table 4 ). the msc8126 device boots from memory that is 8-, 16-, 32-, or 64-bits wide. when an internal memory controller is used, the memory should be attached to cs0 , which functions as the global boot select, and be of a type that the gpcm machine controls (eprom or flash memory). the hrcw[bps] bit sets the width of the cs0 space. after configuration, sc140 core 0 fetches the address of the boot routine from location 0xfe000110. if the msc8126 device boots from a host via the dsi or 60x system bus interface, the host polls the br10[v] bit to determine when the boot program is finished. the host then begins its initialization procedure by loading code and data to the msc8126 device. then it notifies the msc8126 by sending virq1 to sc140 core 0. if the msc8126 device boots via the tdm, the tdm boot master writes blocks of code and data into msc8126 internal memory. the transaction requires the tdm physical layer to be set up and the tdm logical layer handshake to be implemented. the boot master transmits messages to a single msc8126 or multiple msc8126 devices on tdm channel 0. the msc8126 slave devices transmit back to the host on the tdm channel associated with their chip_id . when the tdm session is complete, the valid bit of bank 10 (br10) is set to 1. if the msc8126 device boots from a uart device, a uart boot master writes blocks of code and data into msc8126 internal memory. like the tdm boot option, the transaction requires set up of the physical layer and a uart logical layer handshake. when the uart session is complete, the valid bit of bank 10 (br10) is set to 1. if the msc8126 device boots from an i 2 c slave memory device, it retrieves blocks of code from an external i 2 c device such as a serial eprom. at the end of the i 2 c process, all sc140 cores jump to address 0x0 of their m1 memory. for the boot via tdm, uart, and i 2 c options, the boot code configures the gpio pin multiplexing as required for external communication to boot in these modes. as a result, these gpio configurations become the default pin multiplexing option for the affected signals. for details, see the ?boot program? chapter of the msc8126 reference manual . table 4. boot mode settings bm[0] bm[1] bm[2] boot sequence 0 0 0 external memory on the system bus 0 0 1 external host via dsi or system bus 0 1 0 tdm 0 1 1 uart 1 0 0 i 2 c 1 0 1 reserved 1 1 x reserved
msc8126 design checklist, rev. 6 8 freescale semiconductor bit and byte lane ordering 5 bit and byte lane ordering this section describes the system bus bit and byte lane ordering: ? address/data nomenclature . it is recommended that schematics use documented terminology for the system bus as defined the chapter on ?external signals,? in the msc8126 technical data sheet. ? system bus . the highest-order address bit is a0 . the lowest-order address bit is a[31] . all 32 address pins are valid in a byte access. in a 64-bit access, only the upper 29 a[0?28] address pins are valid, and a[29?31] are driven low. for the 60x data bus, the highest-order data bit is d0 and the lowest order data bit is d63 . ? data byte lane ordering . d[0?7] is the highest-order byte lane on the data bus, and d0 is the highest-order bit of that byte lane. d[0?7] corresponds to write enable 0 ( pwe0 ) and byte lane select 0 ( psddqm0 ). ta b le 5 provides the data byte lane ordering for both the system bus and local bus. ? memory controller byte lanes . the memory controllers can access memories that are 8-, 16-, 32-, and 64-bits wide without creating any ?holes? in the memory space on the system bus. all memories should be placed into the most significant byte lanes as shown in ta b l e 6 . ? flash memory devices . the data lines of most flash memory devices connect to the msc8126 with byte lanes bit-reversed for programming algorithm purposes. a 32-bit example is shown in figure 1 . the figure is correct for a flash simm composed of 8-bit flash devices. adjust the byte lanes as necessary for the memory in your design. the flash memory interface requires a reset input that should connect to the msc8126 poreset . table 5. 60x bus data byte lane ordering data bus signals byte lane external pins (byte lane select) d[0?7] 0 pwe0 / psddqm0 / pbs0 d[8?15] 1 pwe1 / psddqm1 / pbs1 d[16?23] 2 pwe2 / psddqm2 / pbs2 d[24?31] 3 pwe3 / psddqm3 / pbs3 d[32?39] 4 pwe4 / psddqm4 / pbs4 d[40?47] 5 pwe5 / psddqm5 / pbs5 d[48?55] 6 pwe6 / psddqm6 / pbs6 d[56?63] 7 pwe7 / psddqm7 / pbs7 table 6. byte lanes for memory widths memory width byte lanes byte (8-bits) 0 2 bytes (16-bits) 0, 1 4 bytes (32-bits) 0, 1, 2, 3 8 bytes (64-bits) 0, 1, 2, 3, 4, 5, 6, 7
memory msc8126 design checklist, rev. 6 freescale semiconductor 9 figure 1. msc8126 to flash memory byte lane reversal bringing up a board with blank flash memory and no host processor requires a switch or other method to force rstconf to a logic 1 and cnfgs to 0 to bring up the msc8126 in the default state. otherwise, invalid pll values can be loaded. when the device comes out of reset in the default state, the flash memory can be programmed. for subsequent resets, the rstconf and cnfgs signals can be set appropriately for resetting from flash memory. 6memory this section provides design considerations for the msc8126 associated memories. 6.1 60x bus signals and memory transactions the msc8126 is not 5 v tolerant. all input signals must meet v in dc spec (?0.2 v to v ddh + 0.2). ? partial data valid . the memory controller drives psdval for an access to an msc8126-controlled resource (internal space or chip-selects). psdval is used only by external devices that implement the msc8126 memory bank-based bus sizing protocol (for example, an external msc8126). devices that do not implement this memory bank-based bus sizing do not use psdval . ? non-msc8126 masters . msc8126 designs incorporating devices that do not implement the msc8126 memory bank-based bus sizing protocol must either use 64-bit accesses on the system bus or ensure that only msc8126- initiated transactions can access the 8-, 16-, or 32-bit memory mapped slaves on the system bus. ? write enable . pwe[0?7] should be used to control the r/ w lines of memories, due to timing flexibility. for buffer direction control, the bctl[0?1] signals should be used. ? pipelining . the bus can be pipelined up to two address cycles deep. for example, it can have a ts , an aack , and another ts before the first ta . because the address is valid only during the address phase ending with aack , external latches and multiplexes are necessary for sdram, and so on. on accesses to internal slaves, as well as sdram page hits, ta can come before aack . in fact, aack and ta are not guaranteed to be in order. ? single msc8126 mode . the bus operation is the same as for 60x bus mode, except that the address that is driven on a[0?31] is latched and possibly multiplexed inside the msc8126. therefore, the address is valid throughout the data phase of the cycle beginning with aack and ending with the data phase of the next access. single msc8126 mode does not support mastering of the 60x system bus by any other resource, including an additional msc8126 device. d0 d7 d8 d15 d16 d23 d24 d31 d7 d0 d15 d8 d23 d16 d31 d24 msc8126 flash memory
msc8126 design checklist, rev. 6 10 freescale semiconductor eonce/jtag interface ? local bus . the local bus does not burst when an external master accesses it through the 60x bus bridge. accesses to the local bus are not snooped by the sc140 core. ? bursts . burst accesses by 60x masters to registers or to the local bus are terminated with tea . ? address acknowledge . the msc8126 asserts aack for all accesses to external memory that match a br/or range in the memory controller and also drives ta unless programmed otherwise. 6.2 baddrx in 60x mode in 60x-bus-compatible mode, the baddr [27?31] pins must be used?not the standard address a[27?31] pins?to address memories when the gpcm and upm machines are in use. this is necessary because 60x masters, including the internal sc140 core, do not dynamically adjust the transaction for bus size. the 60x masters drive only the starting address on a burst, and thus the address lines do not increment. the gpcm memory controller accesses the memory as single accesses. both the gpcm and the upm increment the baddrx lines to gather the bytes that the 60x master requests. in single msc8126 mode, the memory controllers drive the address lines for small port sizes and increments for bursts. therefore, the baddrx pins are not needed in this mode. 6.3 bank selects versus address lines in single msc8126 mode, use the bnksel lines to interface to sdram to support different sdram densities without requiring board wiring changes. also, use the bnksel lines and set the bcr[eav] bit so that logic analyzers can view the non multiplexed address of the access. 6.4 bank versus page interleaving bank interleaving is the preferred method for connecting to sdram. to achieve the highest performance, the msc8126 sdram machine provides an interface to sdrams using sdram pipelining, bank interleaving, and back-to-back reads or writes in page mode. 7 eonce/jtag interface the msc8126 device includes an enhanced on-chip emulation module (eonce), a feature common to all freescale processors with the sc140 core. eonce gives internal access to scan chains for debug purposes and also provides a serial connection to the sc140 core for emulator support. an eonce/jtag connection adds little or no cost to a system but adds significant advantages during early system development. this interface is implemented using a standard 14-pin header as shown in figure 2 . figure 2. 14-pin header for jtag/eonce interface 12 34 56 78 910 11 12 13 14 tdi tdo nc rst v dd nc gnd gnd gnd key tms nc trst tck
eonce/jtag interface msc8126 design checklist, rev. 6 freescale semiconductor 11 the eonce interface connects through the jtag port on the msc8126 device with some additional status monitoring signals. ta b l e 7 shows the pin definitions and recommendations. connecting multiple devices via their jtag port is commonly called daisy chaining . multiple target dsp devices can connect in series so that a single command converter and jtag connector can control multiple target dsps. daisy chaining should be considered for a board with multiple dsps. in a daisy chain configuration, such as that shown in figure 3 , a serial path is formed by the connection of the serial test data in ( tdi ) and test data out ( tdo ) pins. essentially, the path formed by tdi and tdo connects the jtag registers of the devices serially. the input pin to the entire chain is tdi , and the output pin from the entire chain is tdo . the test clock ( tck ) and test mode select ( tms) pins of all the devices are wired in parallel so that there is a single tck input and a single tms input. in this configuration, if a device in the daisy chain is reset, all devices on the chain are reset because the reset signals are connected. table 7. jtag/eonce interface pin definitions pins connection description recommendations 1 tdi test data in if there are multiple devices on the jtag chain, connect tdi to the tdo signal of the previous device in the chain. 2,4,6 gnd system ground plan connect to digital ground. 3 tdo test data out if there are multiple devices on the jtag chain, connect tdo to the tdi signal of the next device in the chain. 5 tck test clock add a 10 k pull-down resistor. 7,13,12 nc no connect leave unconnected. 8 key mechanical keying pin should be removed. 9 rst reset can be tied to hreset . 10 tms test mode select none. 11 v dd i/o power supply connect to msc8126 i/o voltage v ddh through a 220 current limiting resistor. 14 trst test reset trst has an internal pull-up, so no external pull-up or pull-down is required. however, the recommendation is to add a 1 k pull-down to gnd on this signal to keep the jtag in reset mode while the device is operating normally. asserting this signal asynchronously initializes the test controller. trst must be asserted during power up.
msc8126 design checklist, rev. 6 12 freescale semiconductor signal terminations figure 3. multiple target dsp connection since the msc8126 is a multi-core device, each sc140 core has its own link on the jtag chain. therefore, when you are designing a daisy chain, remember that each msc8126 device provides four indices to the chain. this is also important to remember when you are setting up jtag chain initialization in software. connecting ee0 and ee1 to an additional header is recommended for debug boards. ee0 is used to enter debug mode and ee1 can be used for logic analyzer triggers and other useful debugging activities. refer to the ?debugging? chapter of the msc8126 reference manual for details. 8 signal terminations ta b l e 8 summarizes the signal connections for the msc8126. refer to the data sheet for details on the connection guidelines: ? xx?yy vddh . a pull-up resistor to the v ddh power supply, with a value between xx and yy . you can select the value on the basis of system requirements, such as noise immunity. ? xx?yy gnd . a pull-down resistor to the ground power connection with a value between xx and yy . again, you can specify the value. ?o pen . the signal should/must be left unconnected. the note column in table 8 specifies whether it is a requirement. ? as needed . the connection is determined principally by the system. it connects to the system controller logic, whether from freescale or one of several third-parties who make such logic. if not designated, a pull-up should be between 1k ?10k and connected to v ddh and a pull-down between 100 ?1k and connected to gnd . tdi tdo tms trst reset tck tdi tdo tms trst reset tck tdi tdo tms trst reset tck tdi tdo tms trst reset tck tdi tdo tms trst reset tck td i tdo tck gnd tms trst 1 3 5 2 4 6 8 12 14 7 9 11 13 10 v cc reset nc nc nc nc jtag connector
signal terminations msc8126 design checklist, rev. 6 freescale semiconductor 13 unused inputs should be tied high or low, but not left floating. unused inputs can be tied directly to gnd but a pull-up resistor is recommended if it is tied high. generally, it is good practice to tie any unused input to gnd or v ddh through a resistor for board testability purposes. the following signals are active during the reset configuration period of hreset : a[0?31] , bctl0 , bctl1 , d[0?63] , cs0 , poe , and baddrx . all signals can be turned off using the highz jtag command. input-only signals such as poreset or signals configured in an input-only mode, such as irqx or ext_brx , do not require pull-up/pull-down resistors if they are actively driven. however, in the interest of caution, pull-up resistors are recommended in table 8 . you should exercise discretion. the hard reset signal states provided do not include the states during reset configuration. during the assertion of poreset , configurable signals have their default configuration (and are therefore tri-stated or high impedance). during reset configuration, configurable signals still have their default configuration, and certain memory controller signals operate to perform the reset configuration function ( a[0?31] , bctl0 , bctl1 , d[0?63] , cs0 , poe , baddrx ). table 8. signal states and recommended termination signal function 1 state at hard reset connection notes if used if not used notes: 1. i = input, o = output, b = bidirectional three-state, od = open-drain. most multi-function pins are bidirec - tional three-state. this does not imply that they are all shared signals?only that they can be used as inputs or outputs. br b tri-stated, earb = 0 high, earb = 1 1?10 k v ddh bg b high, earb = 0 tri-stated, earb = 1 1?10 k v ddh open pull up if hrcw[earb] = 1. in single-master mode, no pull-up resistor is required. abb / irq4 b tri-stated 1?10 k v ddh pull up. ts b tri-stated 1?10 k v ddh open pull up. in single-master mode, no pull-up resistor is required. a[0?31] b low as needed open no requirement tt0/ha7 b tri-stated 1?10 k v ddh open pull up in multi-master mode. in single-master mode, no pull-up resistor is required. tt1 b tri-stated 1?10 k v ddh open pull up in multi-master mode. in single-master mode, no pull-up resistor is required. tt[2?4]/ cs[5?7] b tri-stated 1?10 k v ddh open pull up tt[2?4] in multi-master mode. in single-master mode, no pull-up resistor is required. tbst b tri-stated 1?10 k v ddh pull up tsz[0?3] b tri-stated as needed open the tsz bus can be pulled up or down. pull down tsz0 (100 ) for an external master. otherwise, there is no requirement. in single-master mode, these signals can be open. aack b tri-stated 1?10 k v ddh pull up
msc8126 design checklist, rev. 6 14 freescale semiconductor signal terminations artry b tri-stated 1?10 k v ddh pull up dbg b high, earb = 0 tri-stated, earb = 1 1?10 k v ddh open pull up. in single-master mode, no pull-up resistor is required. dbb / irq5 b tri-stated 1?10 k vddh pull up d[0?31] b tri-stated as needed open no requirement hd[32?39]/d[32?39]/ hd[44?45]/d[44?45/] hd[50?53]/d[50?53]/ hd[61?63]/d[61?63] b tri-stated as needed open no requirement hd[40?43]/d[40?43]/ ethrx[0?3] b tri-stated as needed open no requirement hd[46?49]/d[46?49]/ ethtx[0?3] b tri-stated as needed open no requirement hd54/d54/ethtx_en b tri-stated as needed open no requirement hd55/d55/ethtx_er b tri-stated as needed open no requirement hd56/d56/ethrx_dv/et hcrs_dv b tri-stated as needed open no requirement hd57/d57/ethrx_er b tri-stated as needed open no requirement hd58/d58/ethmdc b tri-stated as needed open no requirement hd59/d59/ethmdio b tri-stated as needed open no requirement hd60/d60/ethcol b tri-stated as needed open no requirement ethtx_clk/ ethref_clk i tri-stated as needed pull down ethrx_clk i tri-stated as needed pull down ethcrs i tri-stated as needed pull down dp0/dreq1/ ext_br2 b high, dppc=11 tri-stated otherwise as needed open pull up if used as ext_br2. irq1 /dp1/ dack1 / ext_bg2 b high, dppc =11 tri-stated, otherwise as needed open pull up if used as irq1 or dack1. pull up ext_bg2 in multi-master mode. irq2 /dp2/ dack2 / ext_dbg2 b high, dppc = 11 tri-stated, otherwise as needed open pull up if used as irq2 or dack2. pull up ext_dbg2 in multi-master mode. table 8. signal states and recommended termination (continued) signal function 1 state at hard reset connection notes if used if not used notes: 1. i = input, o = output, b = bidirectional three-state, od = open-drain. most multi-function pins are bidirec- tional three-state. this does not imply that they are all shared signals?only that they can be used as inputs or outputs.
signal terminations msc8126 design checklist, rev. 6 freescale semiconductor 15 irq3 /dp3/dreq2/ ext_br3 b high, dppc = 11 tri-stated, otherwise as needed open pull up if used as irq3 or ext_br3. irq4 /dp4/dack3/ ext_bg3 b high, dppc = 11 tri-stated, otherwise as needed open pull up if used as irq4 or dack3. pull up ext_bg3 in multi-master mode. irq5 /dp5/dack4/ ext_dbg3 b high, dppc = 11 tri-stated, otherwise as needed open pull up if used as irq5 or dack4. pull up ext_dbg3 in multi-master mode. irq6 /dp6/dreq3 b high, dppc = 11 tri-stated, otherwise as needed open pull up if used as irq6 . irq7 /dp7/dreq4 b high, dppc = 11 tri-stated, otherwise as needed open pull up if used as irq7 . psdval b tri-stated 1?10 k v ddh pull up ta b tri-stated 1?10 k v ddh pull up tea b tri-stated 1?10 k v ddh pull up gbl / irq1 b tri-stated 1?10 k v ddh pull up baddr29/ irq5 b low as needed open pull up if used as irq5 . baddr30/ irq2 b low as needed open pull up if used as irq2 . baddr31/ irq3 b low as needed open pull up if used as irq3 . cs[0?4] o high as needed open no requirement bctl1 / cs5 o high as needed open no requirement baddr[27?28] o low as needed open no requirement ale o high as needed open no requirement bctl0 o low as needed open no requirement pwe[0?3] / psddqm[0?3] / pbs[0?3] o high as needed open no requirement psda10/pgpl0 o high as needed open no requirement psdwe /pgpl1 o high as needed open no requirement poe / psdras /pgpl2 o high as needed open no requirement psdcas /pgpl3 o high as needed open no requirement table 8. signal states and recommended termination (continued) signal function 1 state at hard reset connection notes if used if not used notes: 1. i = input, o = output, b = bidirectional three-state, od = open-drain. most multi-function pins are bidirec- tional three-state. this does not imply that they are all shared signals?only that they can be used as inputs or outputs.
msc8126 design checklist, rev. 6 16 freescale semiconductor signal terminations pgta /pupmwait/ ppbs / pgpl4 b tri-stated as needed open pull up if configured as pupmwait or pgta (even when using internal ta). psdamux/pgpl5 o low as needed open no requirement hd0/swte b tri-stated as needed ? pull up or pull down at poreset to enable/disable software watchdog. hd1/dsisync b tri-stated as needed ? pull up or pull down at poreset to enable/disable dsi synchronous mode. hd2/dsi64 b tri-stated as needed ? pull up or pull down at poreset to set the width of the dsi and system buses. hd3/modck1 b tri-stated 10 k ? pull up or pull down per desired clock configuration at poreset . hd4/modck2 b tri-stated 10 k ? pull up or pull down per desired clock configuration at poreset . hd5/cnfgs b tri-stated as required by reset configuration mode ? rstconf and cnfgs define the msc8126 reset configuration mode and should be either pulled up or pulled down at poreset as appropriate for reset mode. for details, see section 4 . hd[6?31] b tri-stated as needed ha[11?29] i tri-stated as needed pull down hwbs[0?3 ]/ hdbs[0?3]/ hwbe[0-3] / hdbe[0?3] i tri-stated as needed pull up pull up when the dsi is in 32-bit or 64-bit data bus mode. hwbs[4?7] / hdbs[4?7] / hwbe[4?7 ]/ hdbe[4?7]/ pwe[4?7] / psddqm[4?7] / pbs[4?7] b tri-stated as needed open pull up when the dsi is in 64-bit data bus mode. hrds /hrw/ hrde i tri-stated as needed pull up or down if not used. hbcs i tri-stated as needed pull up to v ddh when used with a pull up, a 2.2 k pull up is recommended. hta o tri-stated as needed open pull up in synchronous mode. in asynchronous mode, pull up or down, depending on design requirements. when a pull-up resistor is used, the rise time of the hta signal is determined by the pull- up strength until dcr[htaad] is set. table 8. signal states and recommended termination (continued) signal function 1 state at hard reset connection notes if used if not used notes: 1. i = input, o = output, b = bidirectional three-state, od = open-drain. most multi-function pins are bidirec- tional three-state. this does not imply that they are all shared signals?only that they can be used as inputs or outputs.
signal terminations msc8126 design checklist, rev. 6 freescale semiconductor 17 hbrst i tri-stated as needed pull up to v ddh hcid[0?2] i tri-stated as needed pull down hcid[3]/ha8 i tri-stated as needed pull down hclkin i tri-stated as needed pull down hcs i tri-stated as needed pull up to v ddh hdst0/ha9 i tri-stated as needed pull down can be left disconnected if the dsi is in big endian mode. hdst1/ha10 i tri-stated as needed pull down can be left disconnected if the dsi is in big endian mode. gpio0/chip_id0/ irq4 /ethtxd0 b tri-stated as needed pull down configure as needed to define the msc8126 chip id. gpio1/timer0/ irq5 / chip_id1/ ethtxd0 b tri-stated as needed pull down configure as needed to define the msc8126 chip id. gpio2/timer1/ chip_id2/ irq6 b tri-stated as needed pull down configure as needed to define the msc8126 chip id. gpio29/chip_id3/ ethtx_en b tri-stated as needed pull down configure as needed to define the msc8126 chip id. remaining gpio signals b tri-stated as needed pull down leave any unused gpio signals as input and tie them to gnd. nmi i tri-stated 1?10 k v ddh pull up. nmi_out od tri-stated 1?10 k v ddh open pull up if used. irq7 / int_out b high, irq7int=0 otherwise: tri-stated. 1?10 k v ddh open pull up if used. trst i internal pull- up resistor 1 k to gnd see table 7 . tck i tri-stated 1?10 k to gnd see table 7 . tms i internal pull- up resistor 1?10 k to v ddh see table 7 . tdi i internal pull- up resistor 1?10 k to v ddh see table 7 . tdo o tri-stated as needed open see table 7 . test i tri-stated 0 to v ss see table 7 . poreset i tri-stated 1?10 k to v ss weak pull down. table 8. signal states and recommended termination (continued) signal function 1 state at hard reset connection notes if used if not used notes: 1. i = input, o = output, b = bidirectional three-state, od = open-drain. most multi-function pins are bidirec- tional three-state. this does not imply that they are all shared signals?only that they can be used as inputs or outputs.
msc8126 design checklist, rev. 6 18 freescale semiconductor related reading 9 related reading the reference materials listed in table 9 can be obtained at the web site listed on the back cover of this document. visit the relevant product summary page or search by title or document identification number. hreset od low 1?10 k to v ddh pull up. sreset od low 1?10 k ? v ddh pull up. rstconf i tri-stated as required by reset configuration mode ? rstconf and cnfgs define the msc8126 reset configuration mode and should be either pulled-up or pulled-down as appropriate for reset mode. see section 4 for details. ee1 o active as needed open ee0 i active 1?10 k to v ss pull down. bm[0?2/tc[0?2]/ bnksel[0?2] b tri-stated as needed ? pull up or pull down per desired boot mode configuration. clkin i tri-stated as needed ? provide appropriate clock. clkout o active as needed open table 9. related reading document category document title document id data sheet (hardware specifications) msc8126 technical data sheet msc8126 errata (device) msc8126 silicon errata manuals msc8126 reference manual msc8126rm msc8126 user?s guide msc8126ug sc140 dsp core reference manual mnsc140core application notes list available on the website on the back cover of this document reference design msc8126 application development system user?s manual msc8126adsum table 8. signal states and recommended termination (continued) signal function 1 state at hard reset connection notes if used if not used notes: 1. i = input, o = output, b = bidirectional three-state, od = open-drain. most multi-function pins are bidirec- tional three-state. this does not imply that they are all shared signals?only that they can be used as inputs or outputs.
related reading msc8126 design checklist, rev. 6 freescale semiconductor 19
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